The past few decades have been witness to the development of computer systems and their adaptive utility in various domains. The rapid pace of advances in software development and more particularly, the coding schematics used for writing of such computer programs have necessitated increase in processing capacities of the hardware used for execution of these computer programs. There have been significant efforts on two fronts for achieving these objectives. One has been in the development of faster as well as task-specific processors and the other, in the area of re-architecture of computer code for faster execution on available processors.
Parallel computing as a method to enable faster processing of computer programs has been the focus of recent innovations in the art. This has paved the way for the use of multiple processors and of late, processors with multiple processing elements. In this context, the concepts of processor dusters as well as grids deserve mention and multi-processor computers which have multiple processing elements within the same machine.
Though concept of parallel computing seems advantageous and has seen rise in acceptability and popularity amongst software developers, a drawback with this concept becoming the mainstay of the field is that existing methods of programming are sequential and thus not directly suited to parallelising the code. Rewriting such program codes for parallel processing is generally tedious. In addition, identification and mapping of parallelizable portions of the code and intelligent scheduling to different processor elements, remote or otherwise, and also the communication during such processing are still major hurdles towards achieving optimal speed-up of actual execution of computer programs.
Use of multicore processors scores over use of multiple processors in achieving the high processing capacities without requirements of high clock cycles, heat generation and power input. However, with the rising popularity of multicore processors the need for related tools is also increasing. Application developers are in need of tools that could ease the programming for multicore processors. On the other hand, there is also an increased need for tools and methods to parallelize existing computer programs to take optimal advantage of parallel hardware.
In this regard, various prior art literature have attempted parallel execution of sequential computer program code through various means such as: by performing control and data flow analysis to determine parallelizable conditions, determining parallelizable conditions based on class specific abstraction, by using specialized multiple processing units, by converting input source code into intermediate language and then executing task dependency, and by using directed acyclic graphs (DAGs) and post-wait control structures. Another method followed is by accessing data patterns and the profiling information to generate equivalent data access patterns to produce code to control first touch data.
However, there are drawbacks of the methods in the existing prior art such as, in most of the methods human intervention becomes mandatory and the methods concentrates only on the loop parallelization i.e. the part of code which is repeatedly executed. Further, changing the sequential code may temper the actual functionality and also the methods are applicable only to limited range of applications. Furthermore, few methods convert input source code into intermediate language for parallelization which is a tedious process.
Information relevant to attempts to address these problems can be found in U.S. Pat. No. 6,253,371, U.S. Pat. No. 6,243,863, DE 10200505056186, US 20010003187, US 20070234326, US 20070226686, U.S. Pat. No. 6,622,301 and U.S. Pat. No. 6,742,083. However, each one of these references suffers from one or more of the above listed drawbacks.
Therefore, there exists a need for an automated adaptation of legacy code, existing sequential code and new code written in a sequential manner for conversion into code for parallel execution and hence, achieving faster execution on parallel processors. Accordingly, the present invention describes a methods and a system working thereupon for reducing execution times of computer programs by enabling effective parallelization of computer program code thereof.